Модульные насосные приводы: распределение тока и тепловой баланс

Модульные насосные приводы: распределение тока и тепловой баланс

Резюме

Modular pump drivers share load only as well as their passive components match. This article gives the droop arithmetic that sets sharing error, the ESR and thermal coupling terms that dominate it, four field pain points at 15,000 h, and the capacitor and resistor selection that holds ±0.5% matching across 8 units for 50,000 h.

1. Введение

A 20 kW fiber laser needs 24 kW to 28 kW of pump power, split across 8 to 16 identical driver units. Each unit feeds one or two laser diode bars at 30 A to 60 A. Modularity keeps thermal density and field service manageable.

Parallel units act as one source only when they share current. A 2% sharing error shifts optical power between diode bars, and the splice points in the gain fiber absorb the difference as heat. That heat drives fiber degradation, so the laser loses beam quality before it loses power.

Thermal imbalance compounds the electrical problem. Modules on a shared heatsink run at different temperatures, and the passive components that set sharing accuracy age at different rates. The imbalance widens over the 20,000 h to 50,000 h service life.

This article covers the droop model that sets sharing error, the ESR and thermal coupling terms that dominate it, four field pain points, and the component selection that holds ±0.5% matching across a module array for 50,000 h.

2. Основной механизм

2.1 Droop-based current sharing

Each power unit runs as an independent voltage-regulated converter with a droop characteristic:

V_out_i = V_ref − R_droop × I_out_i

where V_out_i is the output voltage of unit i, V_ref the nominal setpoint, R_droop the droop resistance, and I_out_i the output current of that unit.

For N units sharing a total load current I_total, the current in unit i follows:

I_out_i = I_total / N + (V_ref_i − V_ref_avg) / R_droop

where I_total is the total array current, N the number of parallel units, V_ref_i the setpoint of unit i, and V_ref_avg the mean setpoint across the array.

The second term sets the sharing error. Setpoint spread comes from sensing resistor tolerance, capacitor ESR variation, and PCB trace resistance.

2.2 ESR-induced sharing error

The output capacitor ESR adds to the droop resistance of each unit:

R_effective = R_droop + ESR_i

where R_effective is the total droop resistance seen by the load, R_droop the designed droop, and ESR_i the equivalent series resistance of that unit's output capacitors.

For N = 8 units with nominal ESR of 50 mΩ and a ±20% tolerance, the sharing error is:

∆I_share = I_total × (ESR_max − ESR_min) / (N × (R_droop + ESR_nom))

where ∆I_share measures how far one unit departs from its equal share, ESR_max and ESR_min the population extremes, and ESR_nom the nominal value. The 20 mΩ ESR spread against 8 × 100 mΩ of total droop gives 2.5% of I_total, five times the ±0.5% target.

2.3 Thermal coupling between modules

Modules that share a heatsink exchange heat. With a coupling resistance R_th_coupling between neighbours:

∆T_coupling = R_th_coupling × (P_loss_max − P_loss_min)

where ∆T_coupling is the temperature rise one module sees from its neighbour, R_th_coupling the module-to-module thermal resistance, and P_loss_max and P_loss_min the loss extremes in the array. At 0.5 °C/W and a 5 W loss difference, the neighbour rises 2.5 °C.

A resistance that tracks temperature then shifts with it:

∆R / R = TCR × ∆T

where ∆R / R is the fractional resistance change, TCR the temperature coefficient of resistance, and ∆T the temperature excursion. At 50 ppm/°C the 2.5 °C shift moves the resistor by 0.0125%, small alone but cumulative along the thermal chain.

2.4 Capacitor aging sets the drift

Electrolytic capacitance falls and ESR rises with time and temperature. The acceleration follows a ten-degree rule:

Life = L_rated × 2^((T_rated − T_actual) / 10)

where Life is the effective life, L_rated the rated life at rated temperature, T_rated the rated core temperature, and T_actual the operating core temperature. A 5,000 h part rated at 105 °C gives 20,000 h at 85 °C, after which ESR typically doubles and the sharing error of §2.2 grows from 2.5% to 5.0%.

Fig. 1 — A 20 mΩ ESR spread across 8 units grows into a 5% sharing error and a 3–8 °C module gradient, until matched arrays hold it below 0.5%.

3. Проблемы проектирования

Pain Point 1: ESR mismatch between modules

An 8-unit system with 4 electrolytic output capacitors per unit carries 32 capacitors. The ESR population spread reaches ±30% to ±40%, so the effective droop resistance varies by up to 15 mΩ between units and the sharing error lands at 1.5% to 2.0%.

The unit with the lowest ESR carries the most current. It runs hotter, its capacitors age faster, and its ESR falls further away from the array mean. Each cycle widens the gap.

Pain Point 2: Heatsink gradient causes differential aging

In a linear array of 8 modules on a 400 mm heatsink, the end modules run 3 °C to 8 °C cooler than the centre modules. Edge cooling sets that gradient. The centre modules then hold the highest capacitor core temperature and the highest MOSFET on-resistance.

After 15,000 h the centre modules carry 5% to 8% less current than the end modules. The pump power profile across the diode bars is now imbalanced, and no calibration offset corrects it.

Pain Point 3: Sensing resistor placement

A current sensing resistor mounted within 5 mm of a power MOSFET on the same board sits 10 °C to 20 °C above ambient, because the MOSFET junction runs at 100 °C to 120 °C. At a TCR of 50 ppm/°C that moves the resistance by 0.05% to 0.10% per module.

The MOSFET temperature follows load current and switching frequency, so the sensing error changes with operating point. A fixed calibration offset cannot remove it.

Pain Point 4: Gate driver bypass capacitor failure

Each unit needs bypass capacitors at its gate driver ICs. A bypass capacitor that cracks under thermal cycling makes the module's MOSFETs switch erratically or stay off, and that module leaves the array.

The remaining units absorb the lost current, 12.5% more each in an 8-unit array. Overload protection must act within 100 µs, or the surviving modules fail in turn and the pump source shuts down.

4. Этапы проектирования

Strategy 1: Use matched ceramic output arrays

HVC N4700 ceramic capacitors hold ESR within ±5%, against ±20% to ±40% for electrolytics. That limits the ESR term of §2.2 to below 0.5% across 8 parallel modules. Build each unit from 6 to 10 N4700 parts of 2.2 µF at the rated voltage, for combined ESR below 2 mΩ.

The ±5% ESR matching removes the feedback loop of Pain Point 1. No unit gains an ESR advantage, so no unit runs away from the array mean.

Strategy 2: Equalise the heatsink path

Arrange the modules in a symmetrical pattern with identical thermal interface thickness and mounting pressure. Add balance fins between modules to even the airflow. Target less than 3 °C between the hottest and coolest module at full load.

That target needs TIM thermal resistance matched within ±0.1 °C·cm²/W across all modules. Measure it on the first build, because the gradient of Pain Point 2 sets the thermal term of the aging chain.

Strategy 3: Specify low-TCR sensing resistors and Kelvin sensing

Use current sensing resistors with TCR of ±15 ppm/°C or better and four-terminal Kelvin sensing, which removes lead resistance from the measurement. HVC толстопленочный резистор parts hold that TCR in a flat package that sits close to the board.

Mount each sensing resistor on a dedicated thermal pad with controlled resistance to the heatsink. The resistor then tracks heatsink temperature, not MOSFET junction temperature, and stays within ±3 °C across modules for a TCR error of ±0.045%.

Strategy 4: Move bypass capacitors to Class I dielectric

Replace X7R gate driver bypass capacitors with N4700 Class I ceramics. N4700 shows no piezoelectric effect, no DC bias capacitance loss, and no aging-related capacitance loss. The failure rate is below 0.1 FIT, against 1 FIT to 10 FIT for X7R under the same conditions.

That 10× to 100× margin removes the module dropout mode of Pain Point 4. Select the same dielectric for snubber and decoupling positions in the unit, so one part family covers the board.

Strategy 5: Add an average-current sharing bus

Connect all units to a sharing bus. Each unit measures its own output current and compares it to the array average. A slow integrator then trims each unit's voltage setpoint until the currents match.

Set the sharing loop bandwidth between 100 Hz and 1 kHz, well below the switching frequency, so the loop cannot disturb the inner voltage loop. Steady-state sharing error falls below ±0.1%, which covers the residual sensing and trace terms. Pair the loop with резистор выборки parts that hold their value over temperature.

Параметр компонента	Типичное значение	Условие теста
Номинальное напряжение (серия HVCT8G)	10 кВ постоянного тока	высоковольтный режим 1.5× в течение 60 с
емкость	4700 пФ ±20% (472М)	1 МГц, 1 В среднеквадратичное значение
ЭПР на частоте 1 МГц	ниже 50 мОм	-
Индуктивность петли (хорда E40)	ниже 8 нГн	Расстояние между клеммами: 40 мм
сопротивление изоляции	сопротивление выше 10 ГОм при напряжении 500 В постоянного тока	25 ° C, 60% относительной влажности
Диапазон температур	от −40 °C до +125 °C	Серия МЭК 60068-2
Возможность импульсного DV/DT	выше 50 кВ/мкс	при номинальном напряжении

5. HVC N4700 capacitors for modular pump drivers

Three requirements set the choice at this node: a dielectric with no aging drift, low loss in an enclosed module, and matched parameters across every unit in the array. HVC builds N4700 (T3M) Class I parts on a SrTiO3 base for that set, in a 6,000 m² owned factory in Dongguan, across 1 kV to 100 kV.

Шесть параметров, которые здесь имеют значение.

• ESR matching within ±5% across production lots. Against ±20% to ±40% for electrolytics, it limits the ESR-induced sharing error to below 0.5% in an 8-module array with 100 mΩ effective droop.
• Temperature coefficient of ±30 ppm/°C. Capacitance stays within ±0.35% from −55 °C to +125 °C, so a heatsink gradient does not translate into a capacitance difference between modules.
• tan δ of 0.1% or lower. At 2 A rms ripple current one capacitor dissipates under 0.3 W, against 1.5 W to 3.0 W for an electrolytic. Module temperature falls 3 °C to 5 °C and every component in the module gains life.
• No ferroelectric aging. Class II ceramics lose 2% to 5% of capacitance per decade hour; N4700 stays within ±0.5% for the whole product life, so the sharing balance set at commissioning persists past 50,000 h.
• No scheduled replacement. Capacitance stays within 2% after 50,000 h at 85 °C, with intrinsic life beyond 100,000 h, which removes the capacitor from the maintenance window. Coverage runs from 1 kV to 100 kV in radial-lead, screw-terminal, and дверная ручка конденсаторы.
• Qualified as a drop-in for first-tier brands in field-repair programmes, and specified by laser OEMs in new modular platforms. HVC parts match the electrical parameters and package dimensions of Murata высоковольтные компоненты винтового и радиального типов выводов.

Доставка и поддержка

Standard parts ship in 4–8 weeks, and matched custom sets in 6–10 weeks. HVC applications engineering supports sharing simulation, capacitor matching across parallel arrays, thermal analysis, and custom voltage and capacitance combinations.

Send the array current, unit count, droop resistance, heatsink layout, and target matching. HVC returns a matching sheet with part numbers, ESR and capacitance distribution, and a two-sample evaluation kit within five working days.

6. Часто задаваемые вопросы

Q1: How accurate is current sharing across 8 parallel pump driver units?

Within ±0.5% when the output capacitors are matched. An ESR spread of ±20% across 8 units with 50 mΩ nominal ESR and 100 mΩ total droop produces a 2.5% error, which is five times the target. Matched N4700 arrays hold ESR within ±5% and cut the ESR term below 0.5%.

Q2: Why does electrolytic ESR spread matter more than its absolute value?

Because sharing depends on the difference between units, not on the mean. ∆I_share scales with ESR_max − ESR_min against N × (R_droop + ESR_nom). A population spread of 20 mΩ sets the error, so ±30% to ±40% electrolytic grades of Pain Point 1 give 1.5% to 2.0% at array level.

Q3: How much temperature difference can a shared heatsink create?

In a linear array of 8 modules on a 400 mm heatsink, the end modules run 3 °C to 8 °C cooler than the centre modules. After 15,000 h the centre modules carry 5% to 8% less current. A symmetrical layout with TIM matched to ±0.1 °C·cm²/W holds the spread under 3 °C.

Q4: Does sensing resistor placement really shift the sharing balance?

Yes, and the shift is load-dependent. A sensing resistor within 5 mm of a MOSFET junction at 100 °C to 120 °C runs 10 °C to 20 °C above ambient, which at 50 ppm/°C moves it 0.05% to 0.10%. A thermal pad plus a ±15 ppm/°C part holds the module spread to ±3 °C and the error to ±0.045%.

Q5: How long do the output capacitors last in a hot module?

N4700 keeps capacitance within 2% after 50,000 h at 85 °C, with intrinsic life beyond 100,000 h. An electrolytic rated 5,000 h at 105 °C reaches 20,000 h at 85 °C by Life = L_rated × 2^((T_rated − T_actual)/10), and its ESR doubles by then.

Q6: What closes the last fraction of sharing error?

An average-current sharing bus. Each unit compares its output current to the array average, and a slow integrator trims the setpoint. With the loop bandwidth set between 100 Hz and 1 kHz, below the switching frequency, steady-state error falls below ±0.1% and the inner voltage loop stays stable.

7. Рекомендации

1. Э. Куффель, В.С. Заенгль, Дж. Куффель, Основы высоковольтной техники, 2-е изд., Ньюнес, 2000.
2. Н. Мохан, Т.М. Унделанд, У.П. Роббинс, Силовая электроника: преобразователи, применение и дизайн, 3-е изд., Wiley, 2003.
3. Уведомление 2 MIL-HDBK-217F. Прогнозирование надежности электронного оборудования, 1995.
4. МЭК 60384-1:2018, Фиксированные конденсаторы для использования в электронном оборудовании — Часть 1: Общие технические характеристики.
5. Х. Ван и Ф. Блаабьерг, Надежность конденсаторов в силовых электронных преобразователях, использующих звенья постоянного тока: обзор.IEEE Transactions on Industry Applications, том 50, № 5, стр. 3569-3578, 2014. https://doi.org/10.1109/tia.2014.2308357.
6. Б. Ван, Дж. Мэн и П. Чжао, Мониторинг состояния старения алюминиевых электролитических конденсаторов в преобразователях частотыIEEE Transactions on Power Electronics, том 37, № 4, стр. 4564-4574, 2022. https://doi.org/10.1109/tpel.2021.3121813.
7. Заряжая энергией будущее: как высоковольтные многослойные керамические конденсаторы повышают эффективность современной электроникиМурата, https://www.murata.com/en-eu/s/blog/powering-the-future-how-high-voltage-mlccs-drive-efficiency-in-modern-electronics.html .
8. AND9800/D — Выбор демпфирующего конденсатора для применения в системах управления двигателями (таблица 15, данные испытаний), onsemi, AND9800-D, https://m.onsemi.jp/pub/Collateral/AND9800-D.PDF .
9. ГБ/Т 17702-2021, 电力电子电容器 (Конденсаторы для силовой электроники). Пекин: 国家市场监督管理总局, 2021 г.
10. Команда инженеров по разработке приложений HVC, Керамический конденсатор высокого напряжения Тeхничeскиe рeсурсыhttps://www.hv-caps.com